In a semiconductor manufacturing process, integrated circuit chip designers may shrink the design of an IC chip directly. For example, the design of an IC chip may be shrunk from 0.18 μm to 0.16 μm, on the same size of a wafer in a foundry. Some times the design shrink may only apply to part of the process, such as the back-end of a particular process technology. Often as a result of a design shrink, more IC chips can be produced from a single wafer, chip speed or power consumption is improved, and/or other benefits are obtained.
However, the overall cost reduction associated with a design-shrink is not directly evident from the die-area reduction. In particular, the process flow for the prior design may have a better yield percentage. Also, the design-shrink itself may cause problems that need to be resolved—adding to the overall cost. The time it takes for a design shrink to become profitable, referred to as “the interaction time,” may take anywhere from a quarter to a number of years. The interaction time includes the time it takes to develop foundry technologies, silicon-proven learning, and the like. This time-consuming process might make it difficult to realize real benefits, especially with ever-changing business situations.
Determination of the interaction time and chip-area reduction has neither been reliable nor systematic. Thus, an early assessment method on IC design is desired. A valid assessment approach would be beneficial for layout quality index, intelligent property (IP) design, design shrink, and business decision for product cost evaluation.